The present invention relates generally to computer systems, and deals more particularly with high speed access by a computer processor of data from main memory via an intermediary inpage buffer and cache memory.
Computer systems often incorporate large capacity main memories such as RAM or ROM with megabytes of storage capacity. The speed of the processor within such a computer system is typically much faster than the rate at which data can be accessed or fetched from the main memory. The data fetch from the main memory is relatively slow because the main memory is so large that relatively inexpensive semi-conductor technology is used to avoid exorbitant costs. For example, a large main memory may utilize a dynamic random access memory (DRAM) technology whereas a faster, more expensive technology currently available is static random access memory (SRAM). Also, regardless of the technology that is utilized, there are inherent delays in accessing a large memory.
One technique to increase the rate at which data can be accessed by a computer processor from main memory without dramatically increasing the cost of the computer system is to provide a cache memory between the main memory and the processor. The cache memory is a relatively low capacity memory that utilizes the latest, fastest technology (which is more expensive than the main memory per unit of storage). There may also be a low capacity, high speed buffer located between the cache memory and the main memory to participate in the data transfer.
The cache memory is usually local to the processor and contains a time-varying sub-set of the contents of main memory. The cache memory derives its performance enhancement from the principle of locality. According to this principle, over short periods of time, the data required by the processor tends to be clustered in both time and space. In other words, data that will be required in the near future is likely to have been used recently by the processor or located near to the data which was used recently by the processor. In practice, a cache memory can contain a small fraction of the data stored in main memory, yet still have "hit" rates that are extremely high under normal system conditions. Thus, the data that is most likely required by the processor at any time is temporarily stored in the cache memory, and the high speed of the cache memory matches that of the processor.
According to the prior art, the most recent data requested by the processor from main memory can be stored in the cache memory simultaneously with its transfer to the processor. Other data located adjacent to the requested data in main memory is also transferred to the cache memory. Subsequent requests for this data by the processor result in the transfer of data directly from the high speed cache memory to the processor without the need to access the main memory. During operation, when the processor requests data, a directory located in a separate memory and associated with the cache memory is searched. If this search determines that the data is stored in the cache memory, a hit occurs, and the data is transferred to the processor from the cache memory in one or two processor cycles. However, if the requested data is not currently stored in the cache memory, a "miss" occurs, and the data along with other adjacent data is then retrieved from main memory.
Often times, the amount of data that is transferred from main memory to cache memory following a miss is one "line" of data which contains the requested data and additional data located adjacent to the requested data. A main memory "line fetch" or "inpage" operation occurs when the cache memory fetches a line of data from the main memory. A "line castout" or "outpage" operation occurs when a line of data is returned to main memory from the cache memory after modification by the processor to make room for a new line of data in the cache memory.
A line of data is typically 4-16 times longer than the width of a bus between the cache memory and the main memory. Consequently, multiple transfers of data between main memory and cache memory are required to transfer a line of data, and the inpaging of a line of data may take an appreciable amount of time clue to the limitations of the bus. It was previously known as noted above to transmit particular data within a line which is required by the processor directly from the main memory to the processor so that the processor can process the data without waiting for the entire line of data to be transferred first to the cache memory. In this prior art system, the remainder of the line is then inpaged into the cache memory immediately after the direct transfer from main memory to the processor.
European Patent Application 88110696.7 (Publication 304,587 A2) by Thomas L. Jeremiah discloses a system for interrupting loading of data into a cache memory from main memory. A buffering device is connected between main memory and the cache memory for buffering data to be loaded into the cache memory. The buffer receives data from the main memory continuously, and transfers the data to the cache memory continuously unless the cache memory is being accessed by the processor. The processor can access the data from the cache memory before the data transfer from the main memory to the cache memory is completed. Data from the inpage buffer can also be gated through a multiplexer via a bus to the processor to allow early access to data not yet written into the cache memory. In practice, all data from the cache line being inpaged is obtained from the inpage buffer, except for the first access which is bypassed directly from a data register to the processor, until the complete cache line is written into the cache memory and the directory is marked valid.
U.S. Pat. No. 4,953,077 discloses an IBM 4381 computer system (models 23, 24, 91 and 92) comprising a processor 22, main memory 12, and cache memory 14. A controller 18 including a clock 20 controls data transfer directly from main memory 12 to cache memory 14, and a controller 26 with an associated clock 28 controls data transfer between cache memory 14 and processor 22.
In the prior art IBM 4381 computer system (models 23, 24, 91 and 92), the computer processor cannot access the cache memory until a line has been completely loaded from the main memory to the cache memory. The computer system implements an inpage/outpage control sequence referred to as a "fast transfer mode" (FTM) in which the computer processor and the memory/data transfer operate with different sets of clocks. Clocks 20 and 28 of U.S. Pat. No. 4,953,077 have different cycle times.
A general object of the present invention is to improve the speed of access of main memory data by a computer processor.
Another object of the present invention is to provide access of main memory data by a computer processor while permitting the processor and main memory to operate at maximum speed.